First-class guard-nets, -tracks, -zones

[Kenneth L Anderson]

My design needs three different voltage guard traces, and, since there are no design rules to enforce guard trace correctness and thoroughness, a visual inspection in pcbnew is the only way to enforce any rules. It would be so very useful to save the designer's attention span to have an option to alternate with (ramped intensity for calming) highlighting between guard trace and guarded trace in pcbnew's Highlight Net functionality. Like maybe with a 1.5 to 2.0 seconds cycle.

The current means of manually finding/refinding and alternating selections is so tedious for ensuring the guarded traces (of which there could be numerous in my three different stages) are fully guarded throughout their travels and all guarding traces remain fully connected.

Just so the "multiple" word doesn't get overlooked, an example of why multiple stages exist: my guarded traces are high impedance current signals as opposed to voltage signals. First stage operates at 4 VDC, 2nd stage at 1 VDC, 3rd stage at 1.494 VDC fully enclosed by guarding traces at those voltages. I've also had designs using high impedance voltage signals instead of current signals where the guarding traces were supplied by unity-gain buffers. Although only one at a time needs to be examined in pcbnew, I'm just saying there could be multiple of these concurrently in the entire circuit, so allow for that.

[Seth Hillbrand (sethh)]

It would help if you could add a few images of the behavior you are suggesting. At the moment, I can't quite visualize this.

Thanks!

[Kenneth L Anderson (kenneth558)]

screen shot of guarded trace 2 from front side, then its guarding trace

[Kenneth L Anderson (kenneth558)]

guarding trace

[Kenneth L Anderson (kenneth558)]

Here is the schematic view. The source of guarding trace is also shown here

[Jeff Young (jeyjey)]

Perhaps we should even turn this into "Make guard tracks/nets first-class objects". Having to draw them with dotted lines in Eeschema seems a bit error-prone as well.

Or maybe it would be enough to define them in terms of the new rule-based DRC? We don't model differential nets in Eeschema, do we?

Or, maybe we need to make differential nets first-class objects too....

[Kenneth L Anderson (kenneth558)]

Did some searching and see that the guarding trace in schematic form is commonly shown as a dashed line boxing in the guarded trace[s] with a dashed line again showing its connection back to its source. I also see it called a "guard ring". FWIW. I have no experience needing to adhere to any standards about all of it, so getting a handle on this is new to me.

[Kenneth L Anderson (kenneth558)]

It would go a long way simply to allow pcbnew's Highlight Net button to split between an "A" net and a "B" net for now, if the simplicity of that allows a quick and dirty solution.

[Seth Hillbrand (sethh)]

If I'm reading this correctly, Kenneth would like to keep one net highlighted in a different pattern/color while working with or highlighting a second net.

[Kenneth L Anderson (kenneth558)]

I actually was envisioning a button-press-only means of toggling between Net Right and Net Left so you wouldn't have to move the mouse pointer back over to the sometimes tiny spot on a trace that you have had to re-find anyway, then do it all over again to alternate to the other Net.

[Kenneth L Anderson (kenneth558)]

...like simply go back and forth between the two most recent Highlight Net selections

[Kenneth L Anderson (kenneth558)]

...saying it even simpler, Highlight the Net previously Highlighted

[Kenneth L Anderson (kenneth558)]

...which would require one additional button not currently existing...or split the current Highlight Net button in two?

[Jeff Young (jeyjey)]

Well the toggle is certainly easy enough to implement so I went ahead and threw that in.

With that, I'll re-purpose this bug to "make guards first-class citizens".

[Kenneth L Anderson (kenneth558)]

Awesome! I think that is the extent to which I can be of any help with DRC and Eeschema depiction since I'm only standing on the shoulders of others. Except to suggest that during the process of placing/running a guarded trace in pcbnew, enough clearance on the sides of concern would be useful to be enforced: consider situations when

1)the adjacent trace on a specific side must be guarded from (most common), or
2)adjacent trace is inside the same guard ring as spec'd in Eeschema (no extra clearance needed), or
3)an a NPT edge cut can be considered as a functional guard

Such a rule will ensure the guarding trace will fit alongside when laid down in the following step, or could it be (?) trailing the guarded trace in the same pass for case 1.

Thank you!!

[Kenneth L Anderson (kenneth558)]

You'll want to keep in mind for the future that situations like mine can exist where
1) a single guarding net can serve more than one guard ring and
2) it can guard several nets simply because there can be a jumper/resistor/digipot aspect chopping up a net.

Screen shots of that in my situation attached

[Kenneth L Anderson (kenneth558)]

View in pcbnew attached. But for now the quick and easy toggle solution above works wonders better than nothing

[Seth Hillbrand (sethh)]

For future devs looking at this wishlist item, please do not begin implementing this feature without discussing the implementation plan on the developer mailing list.

[Jeff Young (jeyjey)]

Note: you're on your own to find a hotkey you're willing to re-assign to it. If you're running nightlies, just search in the hotkeys for "toggle". It should come up with a few others.

(Oh, and it of course won't be in the nightlies until tomorrow.)

[Kenneth L Anderson (kenneth558)]

Also the layout person can all too easily overlook thorough guarding on the second board side (3rd, etc) when joining the guarded trace to a PTH simply because of the number of simultaneous concerns happening right there sometimes and no DRC rule to assist with catching the other board side(s). The trace on the foreground side can block a person noticing that the other side isn't taken care of.

[Kenneth L Anderson (kenneth558)]

If you want to take it into consideration in developing guard ring DRC, Analog Devices IC designer has this to say about guard traces (from https://www.analog.com/media/en/technical-documentation/data-sheets/AD8244.pdf):

"Remove solder mask from the guard traces to guard against surface leakage due to contamination. In addition to the guard traces on the primary side, route a guard trace around any vias in the input net on the other side of the board as well."

(I already mentioned the second point above, but the bit about removing solder mask was new to me.)

[Kenneth L Anderson (kenneth558)]

(The mention of "input net" above is specific to that component's guard ring, though it actually will apply to what any low output impedance component's guard ring will protect)

[KiCad Janitor (kicad-janitor)]

KiCad bug tracker has moved to Gitlab. This report is now available here: https://gitlab.com/kicad/code/kicad/-/issues/2444