footprint-level DRC exceptions (ie: to disable courtyard checking)
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
KiCad |
Fix Released
|
Unknown
|
Bug Description
I am using a CPU boardlet called the Nanopi NEO2 and made a footprint for it that essentially locates the pin headers on a carrier card for it. These are like supporting beams so the card can hang above the carrier on the two headers. Naturally this footprint has a courtyard. But I also put stuff between the two pin headers underneath the suspended daughter CPU boardlet. I am getting DRC courtyard collisions on scores of small caps used to support a bigger chip on the back side of the carrier. The big chip is on the back side, some of the caps are on the front, the same side as the CPU daughter board.
Is there a way to flag some footprints to be omitted from the courtyard collision tests? Like a hyperspace omission. Without this, I'd have to call this a bug.
Changed in kicad: | |
status: | New → Incomplete |
tags: | added: drc pcbnew |
summary: |
- courtyard collisions + footprint-level DRC exceptions (ie: to disable courtyard checking) |
Changed in kicad: | |
importance: | Wishlist → Unknown |
status: | Expired → Fix Released |
Hi Dick-
Can you make multiple courtyards for the pin headers and let the caps sit between them? I think that the courtyard algorithm allows this.