PNS router doesn't take into account copper layers which have been removed from a PTH.

Bug #1618230 reported by Simon Richter on 2016-08-29
This bug affects 8 people
Affects Status Importance Assigned to Milestone

Bug Description

When a via or thru-hole pad is placed, the inner layers will also receive annular rings, even if there are no connections there. That makes it more difficult to route signals between pins.

Ideally, only clearance from the drill hole would be required on these layers.

PCB Wiz (1-pcb-wiz) wrote :

 Some CAD pgms have a remove unconnected pads option at plot time, but selective re-size for pours, would require a dynamic switch in PAD property, plus additional smarts in Flood to use the drill, if you did not want to use a specific Pad size.
 I think present flood, simply ignores drill/slot.

 Another way to control this, in a less automated manner, would be using the requested PadStack feature.
PadStacks very nearly works now in KiCad - you can define separate Drill & outer size, from F.Cu and B.Cu, and those process ok, but there are small issues around flood and connectivity handling of such Stacks.
It does something, just not quite the correct thing, when it sees concentric Pad Stacks.

 What you cannot yet do, is set an inner size, other than inferred via *.Cu

Some FAB houses like pads defined and to have a minimum annular ring to avoid drill tearing, so a total removal of inner stacks would need some care.

 I can, in present version, create & load a Stack-up fine with larger outer pads (F.Cu,B.Cu) and smaller inner ones (*.Cu) and that works, with the Thermal issue mentioned.

 The Fix required to thermal, is to get it to do 'less work', so it is a conditional removal of action, which should not be too hard to patch in.

PCB Wiz (1-pcb-wiz) wrote :

 Thinking some more about this issue, I think automated removal is complex and risky, but there is a known-defect fix in PcbNew, that could help a lot here.

Fix Required: Allow specific user define of Inner Layer Stacks.

ie make In1.Cu In2.Cu, In*.Cu etc a legal layer specify.

This is quite valid for Traces and Text, but strangely not on Pad Stacks.

Fixing this would allow users to easily shrink the annular ring on inner layers, to give more routing room.
It also gives more choices handling for Flex PCB designs.

Any explicit layer define, should also trump any generic define.

eg *.Cu would define all layers, unless a same-pad define of F.Cu, or In1.Cu, or In*.Cu is seen, in which case the more explicit one, is used instead.
That allows both larger and smaller and even Zero defines, on any Copper layer.
Gives complete user control.

Mask and Paste already work like this - if you add a specific Paste shape/size, that replaces the simpler default of copy-the-copper.

description: updated
tags: added: pcbnew
Jeff Young (jeyjey) wrote :

Note that the Legacy canvas supported this for manually removed layers.

Changed in kicad:
importance: Wishlist → Low
status: New → Triaged
summary: - Reduce impact of thru-hole pads and vias on inner layers
+ PNS router doesn't take into account copper layers which have been
+ removed from a PTH.
tags: added: pns
tags: added: cern
Robert (robee) wrote :

I'd like to add my 2 cents to this item. I might be misunderstanding the title which refers to the push and shove router, but this is an issue for planes and gigabit signals as well. Routing planes out of through hole connectors and under BGAs is seriously degraded by unconnnected internal pads which take up much space. I have to differ with PCB Wiz that having a way to automatically remove these pads is risky as I've found it to be pretty ordinary for manufacturing and is available in other packages.

Tom Williamson (tcwilliamson) wrote :

This has basically canned a project for me unless I find the money to move to Altium...

I've tried using multiple thru-holes on the same location without success

If you set the TH to F&B layers, it will draw the hole without having internal annular rings, however PNS looks at the clearance of the annular rings regardless as a whole, not just the clearances on the inner layer's ring (or lack thereof) still preventing you from operating.

Is there any chance of this being prioritised higher then a 'low'?

Seth Hillbrand (sethh) wrote :

@Tom- Pad stacks are on our road map for v6. No ETA for that.

As a work around, you can stack your pads by placing a THT pad with minimal size directly on top of two SMDs (one for F.Cu and one for B.Cu). This will allow you to route the inner layers more closely than the outer layers.

Be aware that most board houses will require some copper on the annular rings just for runout protection, so I'd avoid making the THT copper too thin.

Pad stacks are on the v6 roadmap.

Changed in kicad:
milestone: none → 6.0.0-rc1
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