Text in on copper layer insufficient clearance between letters

[Chase Rayfield]

Create a ground plane, put some text on it "TT" for example which is the offending part of my logo/copyright notice on my board.

In my case the text is Size X: 0.058 Size Y: 0.058 Thickness: 0.006

Now you will notice that the text has less than 0.005 clearance between the tops of the two Ts. The main issue with this is that the manufacturer I intend to use reports this as a "show stopper" and will likely charge me more to produce that board feature.

I was going to be "smart" and put a keepout area between the tops of the letters but it seems that the text is ignoring the keepout as it still shows up in my gerber files and 3d view. This also occurs at smaller text sizes I imagine if the text is very large it goes away but ideally there should be a way to set the text line clearance between letters.

I imagine the vector font used could be modified as well but that seems like a hack that would end up being forgotten in the long run and liable to regress.

[Nick Østergaard (nickoe)]

What does the manufacturer specify as minimum clearance?

So what you suggest or need is support for letter-spacing (tracking)?

[Chase Rayfield (cusbrar2)]

Quoted from Advanced Circuits's design for manufacturer report:

"We require a minimum of .005" spacing. A premium is charged for spacing or trace width less than .008"."

You can upload gerber files in a zip to FreeDFM.com and it will produce the a report like the one I have here. I uploaded a 2 layer board + top solder mask + top solder paste + top silkscreen + .drl file. And a few other options to complete the form.

[Jeff Young (jeyjey)]

Many fab houses will also complain about text thickness meeting the minimum track width constraint.

The normal way we associate items with design rules is through their net. But text doesn't have a net, and giving it one would be odd at best.

We could say text should obey the Default Netclass, but that's not easily discoverable.

Another idea would be to add another "system" Netclass called "Text", which only has Clearance and Track Width properties.

I'm assigning this a priority of Medium since it can cause unexpected hassles/costs when going to manufacture.

[Jeff Young (jeyjey)]

I thought about this some more, and Net Classes with larger clearances are the domain of higher voltage, while those with larger track widths are the domain of higher currents. The board's classification is only dependent on the -minimum- clearance and track width.

So we could probably just add a minimum clearance to the Global Design Rules, and a checkbox "Text on copper layers must obey minimum clearances / track widths".

BTW: why do we duplicate some of the Global Design Rule options in the DRC Control dialog?

[Wayne Stambaugh (stambaughw)]

On 12/31/2017 11:21 AM, Jeff Young wrote:
> I thought about this some more, and Net Classes with larger clearances
> are the domain of higher voltage, while those with larger track widths
> are the domain of higher currents. The board's classification is only
> dependent on the -minimum- clearance and track width.
>
> So we could probably just add a minimum clearance to the Global Design
> Rules, and a checkbox "Text on copper layers must obey minimum
> clearances / track widths".
>
> BTW: why do we duplicate some of the Global Design Rule options in the
> DRC Control dialog?
>

I'm guessing they allow you to tweak the clearances so you don't have to
exit the DRC dialog. Since I didn't write this code, I am not sure this
is the case.

[Jon Evans (craftyjon)]

IMO the global "minimum track width" should actually be (internally) "minimum feature size" and apply to any objects on copper layer (including text).

[Seth Hillbrand (sethh)]

As long as there is no voltage on the letters, the spacing is immaterial. Advanced circuits will happily allow this type of board but with no guarantees that there won't be shorts between the closer items. I've not encountered a board house that won't manufacture a board because floating copper is too close. The FreeDFM check is automated. If you are worried, just add a note to the User.DWGs layer denoting the exception.

I'd vote for this as won't-fix.

[Wayne Stambaugh (stambaughw)]

@Seth, I think we should consider creating a clearance for any copper objects not connected to a net rather than just ignoring it. We may want to set the priority to wishlist since technically we are not violating any net clearances and this would be a new feature.

[Jeff Young (jeyjey)]

Moving to the DFM bucket.