[Feature] Cristal Ridge: x86 Process Context IDentifiers (PCID) support for OSV
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
intel |
Won't Fix
|
Undecided
|
Unassigned | ||
linux (Ubuntu) |
Incomplete
|
Medium
|
Seth Forshee |
Bug Description
Description:
The mapping from virtual address to physical address will be stored in someplace called TLB,
CPU need to occasionally flush TLB for different reasons, the flush will impact all process address mapping,
with PCID support, the impact will be minimal, this will bring overcall performance boost.
The commits comes from Andy Lutomirski(not Intel), which is quite recent, on July 5 2017.
Part1:
660da7c9228f x86/mm: Enable CR4.PCIDE on supported systems
0790c9aad849 x86/mm: Add the 'nopcid' boot option to turn off PCID
cba4671af755 x86/mm: Disable PCID on 32-bit kernels
43858b4f25cf x86/mm: Stop calling leave_mm() in idle code
94b1b03b519b x86/mm: Rework lazy TLB mode and TLB freshness tracking
b0579ade7cd8 x86/mm: Track the TLB's tlb_gen and update the flushing algorithm
f39681ed0f48 x86/mm: Give each mm TLB flush generation a unique ID
Part2:
10af6235e0d3 x86/mm: Implement PCID based optimization: try to preserve old TLB entries using PCID
Target Release: 17.10
Kernel: 4.14
information type: | Proprietary → Public |
Changed in linux (Ubuntu): | |
assignee: | nobody → Seth Forshee (sforshee) |
importance: | Undecided → Medium |
status: | New → Triaged |
@Canonical if the effort is little, just backport it. Thx