diff -u xserver-xorg-video-mga-1.4.11.dfsg/debian/control xserver-xorg-video-mga-1.4.11.dfsg/debian/control --- xserver-xorg-video-mga-1.4.11.dfsg/debian/control +++ xserver-xorg-video-mga-1.4.11.dfsg/debian/control @@ -1,7 +1,8 @@ Source: xserver-xorg-video-mga Section: x11 Priority: optional -Maintainer: Debian X Strike Force +Maintainer: Ubuntu Developers +XSBC-Original-Maintainer: Debian X Strike Force Uploaders: David Nusinow , Brice Goglin , Julien Cristau Build-Depends: debhelper (>= 5.0.0), diff -u xserver-xorg-video-mga-1.4.11.dfsg/debian/changelog xserver-xorg-video-mga-1.4.11.dfsg/debian/changelog --- xserver-xorg-video-mga-1.4.11.dfsg/debian/changelog +++ xserver-xorg-video-mga-1.4.11.dfsg/debian/changelog @@ -1,3 +1,11 @@ +xserver-xorg-video-mga (1:1.4.11.dfsg-2ubuntu1) lucid; urgency=low + + * debian/patches/100_add_200EH_support.patch: + + Patch taken from upstream git to add support for G200EH cards + (LP: #546149) + + -- Christopher James Halse Rogers Wed, 31 Mar 2010 11:33:30 +1100 + xserver-xorg-video-mga (1:1.4.11.dfsg-2) experimental; urgency=low [ Timo Aaltonen ] diff -u xserver-xorg-video-mga-1.4.11.dfsg/debian/patches/series xserver-xorg-video-mga-1.4.11.dfsg/debian/patches/series --- xserver-xorg-video-mga-1.4.11.dfsg/debian/patches/series +++ xserver-xorg-video-mga-1.4.11.dfsg/debian/patches/series @@ -1,0 +2 @@ +100_add_200EH_support.patch only in patch2: unchanged: --- xserver-xorg-video-mga-1.4.11.dfsg.orig/debian/patches/100_add_200EH_support.patch +++ xserver-xorg-video-mga-1.4.11.dfsg/debian/patches/100_add_200EH_support.patch @@ -0,0 +1,428 @@ +commit 3f215b64889bcc7a656fc36db1eed8276b401a95 +Author: Yannick Heneault +Date: Thu Feb 11 11:37:36 2010 -0500 + + Added support for G200EH + +diff --git a/src/mga.h b/src/mga.h +index 18652a8..2cb3d88 100644 +--- a/src/mga.h ++++ b/src/mga.h +@@ -133,6 +133,10 @@ void MGAdbg_outreg32(ScrnInfoPtr, int,int, char*); + #define PCI_CHIP_MGAG200_EV_PCI 0x0530 + #endif + ++#ifndef PCI_CHIP_MGAG200_EH_PCI ++#define PCI_CHIP_MGAG200_EH_PCI 0x0533 ++#endif ++ + /* + * Read/write to the DAC via MMIO + */ +@@ -474,6 +478,7 @@ typedef struct { + int is_G200SE:1; + int is_G200WB:1; + int is_G200EV:1; ++ int is_G200EH:1; + + int KVM; + +diff --git a/src/mga_dacG.c b/src/mga_dacG.c +index 7d4cbfb..df00765 100644 +--- a/src/mga_dacG.c ++++ b/src/mga_dacG.c +@@ -211,6 +211,55 @@ MGAG200WBComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) + } + + static void ++MGAG200EHComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) ++{ ++ unsigned int ulComputedFo; ++ unsigned int ulFDelta; ++ unsigned int ulFPermitedDelta; ++ unsigned int ulFTmpDelta; ++ unsigned int ulTestP; ++ unsigned int ulTestM; ++ unsigned int ulTestN; ++ unsigned int ulVCOMax; ++ unsigned int ulVCOMin; ++ unsigned int ulPLLFreqRef; ++ ++ ulVCOMax = 800000; ++ ulVCOMin = 400000; ++ ulPLLFreqRef = 33333; ++ ++ ulFDelta = 0xFFFFFFFF; ++ /* Permited delta is 0.5% as VESA Specification */ ++ ulFPermitedDelta = lFo * 5 / 1000; ++ ++ /* Then we need to minimize the M while staying within 0.5% */ ++ for (ulTestP = 16; ulTestP > 0; ulTestP>>= 1) { ++ if ((lFo * ulTestP) > ulVCOMax) continue; ++ if ((lFo * ulTestP) < ulVCOMin) continue; ++ ++ for (ulTestM = 1; ulTestM <= 32; ulTestM++) { ++ for (ulTestN = 17; ulTestN <= 256; ulTestN++) { ++ ulComputedFo = (ulPLLFreqRef * ulTestN) / (ulTestM * ulTestP); ++ if (ulComputedFo > lFo) ++ ulFTmpDelta = ulComputedFo - lFo; ++ else ++ ulFTmpDelta = lFo - ulComputedFo; ++ ++ if (ulFTmpDelta < ulFDelta) { ++ ulFDelta = ulFTmpDelta; ++ *M = (CARD8)(ulTestM - 1); ++ *N = (CARD8)(ulTestN - 1); ++ *P = (CARD8)(ulTestP - 1); ++ } ++ ++ if ((lFo * ulTestP) >= 600000) ++ *P |= 0x80; ++ } ++ } ++ } ++} ++ ++static void + MGAG200EVPIXPLLSET(ScrnInfoPtr pScrn, MGARegPtr mgaReg) + { + MGAPtr pMga = MGAPTR(pScrn); +@@ -483,6 +532,89 @@ MGAG200WBRestoreFromModeSwitch(ScrnInfoPtr pScrn) + outMGAdac(MGA1064_GEN_IO_DATA, ucTmpData); + } + ++static void ++MGAG200EHPIXPLLSET(ScrnInfoPtr pScrn, MGARegPtr mgaReg) ++{ ++ MGAPtr pMga = MGAPTR(pScrn); ++ ++ unsigned long ulFallBackCounter, ulLoopCount, ulLockCheckIterations = 0, ulTempCount, ulVCount; ++ unsigned char ucTempByte, ucPixCtrl, ucPLLLocked = FALSE; ++ unsigned char ucM; ++ unsigned char ucN; ++ unsigned char ucP; ++ unsigned char ucS; ++ ++ while(ulLockCheckIterations <= 32 && ucPLLLocked == FALSE) ++ { ++ // Set pixclkdis to 1 ++ ucPixCtrl = inMGAdac(MGA1064_PIX_CLK_CTL); ++ ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_DIS; ++ outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); ++ ++ // Select PLL Set C ++ ucTempByte = INREG8(MGAREG_MEM_MISC_READ); ++ ucTempByte |= 0x3<<2; //select MGA pixel clock ++ OUTREG8(MGAREG_MEM_MISC_WRITE, ucTempByte); ++ ++ ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; ++ ucPixCtrl &= ~0x80; ++ outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); ++ ++ // Wait 500 us ++ usleep(500); ++ ++ // Program the Pixel PLL Register ++ outMGAdac(MGA1064_EH_PIX_PLLC_N, mgaReg->PllN); ++ outMGAdac(MGA1064_EH_PIX_PLLC_M, mgaReg->PllM); ++ outMGAdac(MGA1064_EH_PIX_PLLC_P, mgaReg->PllP); ++ ++ // Wait 500 us ++ usleep(500); ++ ++ // Select the pixel PLL by setting pixclksel to 1 ++ ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); ++ ucTempByte &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; ++ ucTempByte |= MGA1064_PIX_CLK_CTL_SEL_PLL; ++ outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); ++ ++ // Reset dotclock rate bit. ++ OUTREG8(MGAREG_SEQ_INDEX, 1); ++ ucTempByte = INREG8(MGAREG_SEQ_DATA); ++ OUTREG8(MGAREG_SEQ_DATA, ucTempByte & ~0x8); ++ ++ // Set pixclkdis to 0 and pixplldn to 0 ++ ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); ++ ucTempByte &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; ++ ucTempByte &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; ++ outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); ++ ++ // Poll VCount. If it increments twice inside 150us, ++ // we assume that the PLL has locked. ++ ulLoopCount = 0; ++ ulVCount = INREG(MGAREG_VCOUNT); ++ ++ while(ulLoopCount < 30 && ucPLLLocked == FALSE) ++ { ++ ulTempCount = INREG(MGAREG_VCOUNT); ++ ++ if(ulTempCount < ulVCount) ++ { ++ ulVCount = 0; ++ } ++ if ((ucTempByte - ulVCount) > 2) ++ { ++ ucPLLLocked = TRUE; ++ } ++ else ++ { ++ usleep(5); ++ } ++ ulLoopCount++; ++ } ++ ulLockCheckIterations++; ++ } ++} ++ + /** + * Calculate the PLL settings (m, n, p, s). + * +@@ -631,6 +763,12 @@ MGAGSetPCLK( ScrnInfoPtr pScrn, long f_out ) + pReg->PllM = m; + pReg->PllN = n; + pReg->PllP = p; ++ } else if (pMga->is_G200EH) { ++ MGAG200EHComputePLLParam(pScrn, f_out, &m, &n, &p); ++ ++ pReg->PllM = m; ++ pReg->PllN = n; ++ pReg->PllP = p; + } else { + /* Do the calculations for m, n, p and s */ + MGAGCalcClock( pScrn, f_out, &m, &n, &p, &s ); +@@ -828,6 +966,15 @@ MGAGInit(ScrnInfoPtr pScrn, DisplayModePtr mode) + pReg->Option2 = 0x0000b000; + break; + ++ case PCI_CHIP_MGAG200_EH_PCI: ++ pReg->DacRegs[MGA1064_MISC_CTL] = ++ MGA1064_MISC_CTL_VGA8 | ++ MGA1064_MISC_CTL_DAC_RAM_CS; ++ ++ pReg->Option = 0x00000120; ++ pReg->Option2 = 0x0000b000; ++ break; ++ + case PCI_CHIP_MGAG200: + case PCI_CHIP_MGAG200_PCI: + default: +@@ -1177,7 +1324,7 @@ MGA_NOT_HAL( + if (pMga->is_G200SE + && ((i == 0x2C) || (i == 0x2D) || (i == 0x2E))) + continue; +- if ( (pMga->is_G200EV || pMga->is_G200WB) && ++ if ( (pMga->is_G200EV || pMga->is_G200WB || pMga->is_G200EH) && + (i >= 0x44) && (i <= 0x4E)) + continue; + +@@ -1218,6 +1365,8 @@ MGA_NOT_HAL( + MGAG200EVPIXPLLSET(pScrn, mgaReg); + } else if (pMga->is_G200WB) { + MGAG200WBPIXPLLSET(pScrn, mgaReg); ++ } else if (pMga->is_G200EH) { ++ MGAG200EHPIXPLLSET(pScrn, mgaReg); + } + ); /* MGA_NOT_HAL */ + #ifdef USEMGAHAL +@@ -1402,6 +1551,10 @@ MGAGSave(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, MGARegPtr mgaReg, + mgaReg->PllM = inMGAdac(MGA1064_EV_PIX_PLLC_M); + mgaReg->PllN = inMGAdac(MGA1064_EV_PIX_PLLC_N); + mgaReg->PllP = inMGAdac(MGA1064_EV_PIX_PLLC_P); ++ } else if (pMga->is_G200EH) { ++ mgaReg->PllM = inMGAdac(MGA1064_EH_PIX_PLLC_M); ++ mgaReg->PllN = inMGAdac(MGA1064_EH_PIX_PLLC_N); ++ mgaReg->PllP = inMGAdac(MGA1064_EH_PIX_PLLC_P); + } + + mgaReg->PIXPLLCSaved = TRUE; +@@ -1584,6 +1737,7 @@ static const struct mgag_i2c_private { + { (1 << 0), (1 << 2) }, + { (1 << 4), (1 << 5) }, + { (1 << 0), (1 << 1) }, /* G200SE, G200EV and G200WB I2C bits */ ++ { (1 << 1), (1 << 0) }, /* G200EH I2C bits */ + }; + + +@@ -1596,6 +1750,8 @@ MGAG_ddc1Read(ScrnInfoPtr pScrn) + + if (pMga->is_G200SE || pMga->is_G200WB || pMga->is_G200EV) + i2c_index = 3; ++ else if (pMga->is_G200EH) ++ i2c_index = 4; + else + i2c_index = 0; + +@@ -1695,6 +1851,8 @@ MGAG_i2cInit(ScrnInfoPtr pScrn) + + if (pMga->is_G200SE || pMga->is_G200WB || pMga->is_G200EV) + i2c_index = 3; ++ else if (pMga->is_G200EH) ++ i2c_index = 4; + else + i2c_index = 0; + +diff --git a/src/mga_driver.c b/src/mga_driver.c +index e0b724b..2922d2c 100644 +--- a/src/mga_driver.c ++++ b/src/mga_driver.c +@@ -388,6 +388,22 @@ static const struct mga_device_attributes attribs[] = { + 8192, 0x4000, /* Memory probe size & offset values */ + }, + ++ /* G200EH */ ++ [14] = { 0, 1, 0, 0, 1, 0, 0, 0, new_BARs, ++ (TRANSC_SOLID_FILL | TWO_PASS_COLOR_EXPAND | USE_LINEAR_EXPANSION), ++ { ++ { 50000, 230000 }, /* System VCO frequencies */ ++ { 50000, 203400 }, /* Pixel VCO frequencies */ ++ { 0, 0 }, /* Video VCO frequencies */ ++ 45000, /* Memory clock */ ++ 27050, /* PLL reference frequency */ ++ 0, /* Supports fast bitblt? */ ++ MGA_HOST_PCI /* Host interface */ ++ }, ++ ++ 8192, 0x4000, /* Memory probe size & offset values */ ++ }, ++ + }; + + #ifdef XSERVER_LIBPCIACCESS +@@ -415,6 +431,8 @@ static const struct pci_id_match mga_device_match[] = { + + MGA_DEVICE_MATCH( PCI_CHIP_MGAG200_WINBOND_PCI, 13 ), + ++ MGA_DEVICE_MATCH( PCI_CHIP_MGAG200_EH_PCI, 14 ), ++ + { 0, 0, 0 }, + }; + #endif +@@ -433,6 +451,7 @@ static SymTabRec MGAChipsets[] = { + { PCI_CHIP_MGAG200_SE_B_PCI, "mgag200 SE B PCI" }, + { PCI_CHIP_MGAG200_EV_PCI, "mgag200 EV Maxim" }, + { PCI_CHIP_MGAG200_WINBOND_PCI, "mgag200 eW Nuvoton" }, ++ { PCI_CHIP_MGAG200_EH_PCI, "mgag200eH" }, + { PCI_CHIP_MGAG400, "mgag400" }, + { PCI_CHIP_MGAG550, "mgag550" }, + {-1, NULL } +@@ -455,6 +474,8 @@ static PciChipsets MGAPciChipsets[] = { + RES_SHARED_VGA }, + { PCI_CHIP_MGAG200_WINBOND_PCI, PCI_CHIP_MGAG200_WINBOND_PCI, + RES_SHARED_VGA }, ++ { PCI_CHIP_MGAG200_EH_PCI, PCI_CHIP_MGAG200_EH_PCI, ++ RES_SHARED_VGA }, + { PCI_CHIP_MGAG400, PCI_CHIP_MGAG400, RES_SHARED_VGA }, + { PCI_CHIP_MGAG550, PCI_CHIP_MGAG550, RES_SHARED_VGA }, + { -1, -1, RES_UNDEFINED } +@@ -889,6 +910,10 @@ MGAProbe(DriverPtr drv, int flags) + attrib_no = 13; + break; + ++ case PCI_CHIP_MGAG200_EH_PCI: ++ attrib_no = 14; ++ break; ++ + default: + return FALSE; + } +@@ -1112,7 +1137,7 @@ MGACountRam(ScrnInfoPtr pScrn) + OUTREG8(MGAREG_CRTCEXT_DATA, tmp | 0x80); + + /* apparently the G200 IP don't have a BIOS to read */ +- if (pMga->is_G200SE || pMga->is_G200EV || pMga->is_G200WB) { ++ if (pMga->is_G200SE || pMga->is_G200EV || pMga->is_G200WB || pMga->is_G200EH) { + CARD32 MemoryAt0, MemoryAt1, Offset; + CARD32 FirstMemoryVal1, FirstMemoryVal2; + CARD32 SecondMemoryVal1, SecondMemoryVal2; +@@ -1594,6 +1619,7 @@ MGAPreInit(ScrnInfoPtr pScrn, int flags) + || (pMga->Chipset == PCI_CHIP_MGAG200_SE_B_PCI); + pMga->is_G200EV = (pMga->Chipset == PCI_CHIP_MGAG200_EV_PCI); + pMga->is_G200WB = (pMga->Chipset == PCI_CHIP_MGAG200_WINBOND_PCI); ++ pMga->is_G200EH = (pMga->Chipset == PCI_CHIP_MGAG200_EH_PCI); + + #ifdef USEMGAHAL + if (pMga->chip_attribs->HAL_chipset) { +@@ -2115,6 +2141,7 @@ MGAPreInit(ScrnInfoPtr pScrn, int flags) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + case PCI_CHIP_MGAG400: + case PCI_CHIP_MGAG550: + MGAGSetupFuncs(pScrn); +@@ -2227,6 +2254,7 @@ MGAPreInit(ScrnInfoPtr pScrn, int flags) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + pMga->SrcOrg = 0; + pMga->DstOrg = 0; + break; +@@ -2413,6 +2441,7 @@ MGAPreInit(ScrnInfoPtr pScrn, int flags) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + case PCI_CHIP_MGAG400: + case PCI_CHIP_MGAG550: + maxPitch = 4096; +@@ -4316,7 +4345,10 @@ MGAValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags) + return MODE_BANDWIDTH; + } else if (pMga->is_G200EV + && (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 327)) { +- return MODE_BANDWIDTH; ++ return MODE_BANDWIDTH; ++ } else if (pMga->is_G200EH ++ && (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 375)) { ++ return MODE_BANDWIDTH; + } + + lace = 1 + ((mode->Flags & V_INTERLACE) != 0); +diff --git a/src/mga_merge.c b/src/mga_merge.c +index 4cfa0a7..753f752 100644 +--- a/src/mga_merge.c ++++ b/src/mga_merge.c +@@ -362,6 +362,7 @@ MGAPreInitMergedFB(ScrnInfoPtr pScrn1, int flags) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + case PCI_CHIP_MGAG400: + case PCI_CHIP_MGAG550: + MGAGSetupFuncs(pScrn); +@@ -516,6 +517,7 @@ MGAPreInitMergedFB(ScrnInfoPtr pScrn1, int flags) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + case PCI_CHIP_MGAG400: + case PCI_CHIP_MGAG550: + maxPitch = 4096; +diff --git a/src/mga_reg.h b/src/mga_reg.h +index 6450e2f..6251976 100644 +--- a/src/mga_reg.h ++++ b/src/mga_reg.h +@@ -432,6 +432,11 @@ + #define MGA1064_EV_PIX_PLLC_N 0xb7 + #define MGA1064_EV_PIX_PLLC_P 0xb8 + ++/* Modified PLL for G200 EH */ ++#define MGA1064_EH_PIX_PLLC_M 0xb6 ++#define MGA1064_EH_PIX_PLLC_N 0xb7 ++#define MGA1064_EH_PIX_PLLC_P 0xb8 ++ + + #define MGA1064_DISP_CTL 0x8a + #define MGA1064_DISP_CTL_DAC1OUTSEL_MASK 0x01 +diff --git a/src/mga_storm.c b/src/mga_storm.c +index 0d04c63..87473c8 100644 +--- a/src/mga_storm.c ++++ b/src/mga_storm.c +@@ -1130,6 +1130,7 @@ void MGAStormEngineInit( ScrnInfoPtr pScrn ) + case PCI_CHIP_MGAG200_SE_B_PCI: + case PCI_CHIP_MGAG200_WINBOND_PCI: + case PCI_CHIP_MGAG200_EV_PCI: ++ case PCI_CHIP_MGAG200_EH_PCI: + pMga->SrcOrg = 0; + OUTREG(MGAREG_SRCORG, pMga->realSrcOrg); + OUTREG(MGAREG_DSTORG, pMga->DstOrg);