various issues with busses in Verilog back end

Bug #698462 reported by jetrull on 2007-06-22
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
gEDA
Undecided
Unassigned

Bug Description

I know of three problems with the Verilog back end related to bussed wires and I/Os:

1) bussed outputs appear in the port listing twice: once as inputs, once as outputs
2) single-bit busses whose only bit is 0 appear as scalars without an index in the port list
3) instance names with square brackets are not escaped

An example schematic is attached.

Regards,
Jeff Trull

jetrull (jetrull-users) wrote :
jetrull (jetrull-users) wrote :
Peter TB Brett (peter-b) on 2011-01-07
tags: added: gnetlist
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