A64 inline assembly register width selection

[Christopher Covington]

The following code snippet fails to compile:

int main() {
  int ret;
  long a=0, b=1;

  __asm__ volatile (
    "stxr %0, %2, [%1] \n\t"
    :"=&r" (ret)
    :"r" (&a), "r" (b)
    : "memory"
  );

  return ret;
}

Error: operand mismatch -- `stxr x0,x2,[x1]'

This can be worked around by manually using a 32-bit wide register such as the following.

int main() {
  register int ret asm("w2");
  long a=0, b=1;

  __asm__ volatile (
    "stxr w2, %2, [%1] \n\t"
    :"=&r" (ret)
    :"r" (&a), "r" (b)
    : "memory"
  );

  return ret;
}

However it would be better if this didn't have to be worked around and instead the tools would select the proper form of the register for based on instruction limitations. If that is not possible/reasonable, then a constraint that provides an explicit register width to use for a parameter would be helpful, such as:

"=&rw" (ret)

[Yvan Roux (yvan-roux)]

Hi Christopher,

you can explicitly constraint the register width like that :

"stxr %w0, %2, [%1] \n\t"

Yvan

[Christopher Covington (cov-k)]

Thanks! That workaround is much cleaner. Is it documented anywhere?

[Yvan Roux (yvan-roux)]

Well... you can give a look at the " Mode attributes" section in gcc/config/aarch64/iterators.md,
I don't know if it is more "documented" elsewhere ;)

[Maxim Kuvyrkov (maxim-kuvyrkov)]

Yvan,

Do you think this worth documenting in GCC manual? Or is this a rare-enough occurrence that we can leave it here in launchpad?

Thank you.

[Yvan Roux (yvan-roux)]

As lot of the assembly instructions of AArch64 ISA support both variants I guess that the need to enforce the mode when using asm statements will happen quite often. So, maybe adding something in the manual in would be helpful.

[Christopher Covington (cov-k)]

Is it not possible for the smaller width to be automatically used?

[Yvan Roux (yvan-roux)]

Now tracked at https://bugs.linaro.org/show_bug.cgi?id=414