Cortex-M0: Wrong registers in inline asm
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
GNU Arm Embedded Toolchain |
Invalid
|
Undecided
|
Unassigned |
Bug Description
Version:gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc
The compiler uses illegal registers for inline assembly.
Example:
static int MULSHIFT32(int a, int b)
{
short t0,t1,t2;
__asm__ volatile (
" .syntax unified\n"
"uxth %2,%0 // b\n"
"lsrs %0,%0,#16 // a\n"
"lsrs %3,%1,#16 // c\n"
"uxth %1,%1 // d\n"
"movs %4,%1 // d\n"
"mul %1,%2 // bd\n"
"mul %4,%0 // ad\n"
"mul %0,%3 // ac\n"
"mul %3,%2 // bc\n"
"lsls %2,%4,#16 // ad => d0\n"
"lsrs %4,%4,#16 // ad => 0ay"
"adds %1,%1,%2 // bd + d0\n"
"adcs %0,%4 // ac + 0a + C\n"
"lsls %2,%3,#16 // bc => c0\n"
"lsrs %3,%3,#16 // bc => 0b\n"
"adds %1,%1,%2 // bd + c0\n"
"adcs %0,%3 // ac + 0b + C\n"
return a;
}
Generated code:
.syntax unified
uxth r6,r4 // b
lsrs r4,r4,#16 // a
lsrs r7,r5,#16 // c
uxth r5,r5 // d
movs ip,r5 // d
mul r5,r6 // bd
mul ip,r4 // ad
mul r4,r7 // ac
mul r7,r6 // bc
lsls r6,ip,#16 // ad => d0
lsrs ip,ip,#16 // ad => 0ayadds r5,r5,r6 // bd + d0
adcs r4,ip // ac + 0a + C
lsls r6,r7,#16 // bc => c0
lsrs r7,r7,#16 // bc => 0b
adds r5,r5,r6 // bd + c0
adcs r4,r7 // ac + 0b + C
(IP is r12, but only registers r0..7 are allowed)
Test source attached.
Compile options: -S -mthumb -mcpu=cortex-m0 -O2