use of local register after function epilogue

[Andrew Malachowski]

I've verified the bug exists when compiling with -O2 optimizations targeting the Cortex M4 family using the binary packaged 5.4.1 20160609 and 5.3.1 20160307 releases and that disabling -foptimize-sibling-calls corrects the behavior. I've attached the source used to generate the snippet below and found that adjusting the number of members initialized causes the compiler to adjust the register allocation which allows for correct code generation.

test:
 @ args = 0, pretend = 0, frame = 0
 @ frame_needed = 0, uses_anonymous_args = 0
 push {r3, r4, r5, lr}
 ldr r4, .L8
 ldr r5, .L8+4
 movs r2, #32
 mov r0, r4
 movs r1, #0
 bl memset
 ldr r3, .L8+8
 ldr r0, .L8+12
 ldr r1, .L8+16
 ldr r2, .L8+20
 str r5, [r4]
 str r0, [r4, #4]
 str r1, [r4, #8]
 str r2, [r4, #12]
 str r3, [r4, #16]
 pop {r3, r4, r5, lr}
 bx r3 @ indirect register sibling call

[Andre Vieira (andre-simoesdiasvieira)]

Hi Andrew,

Sorry for the delay, I can confirm this. This also reveals another issue, the value that is in r3 (if we ignore the pop) is the address to callback4. This seems to originate from the middle end and I have confirmed it on both ARM and AARCH64, might be an issue with other targets too.

I am working on a bug report for the latter issue. As for the issue you reported, it seems to be working on trunk, so I will have a look at whether that is just coincidence or whether it has been fixed and needs a backport. Unfortunately I do not think we will be able to get this in for the next update release.

I see that our 4.9 2015q3 release does not have either of these issues, could you use that for the time being?

Kind Regards,
Andre

[Andre Vieira (andre-simoesdiasvieira)]

Ignore that one, calling callback4 there is fine, since GCC has detected that they are all the same. Ill look into the pop issue now.

[Andrew Malachowski (andrew-malachowski)]

Andre,

Rolling back to the 4.9 2015q3 release is no problem.

Thanks,
-Andrew