Convert Verilog Generation to Generator Interface
Bug #991865 reported by
Richard Leys
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| FSMDesigner |
Fix Released
|
High
|
Richard Leys | ||
Bug Description
The API should provide a Generator Interface, to allow transforming an FSM to a certain output.
Add a Generator interface and Factory.
Generators should output to an output stream.
Revision history for this message
| Richard Leys (richard-leys) wrote | #1 |
| Changed in fsmdesigner: | |
| status: | New → In Progress |
| Changed in fsmdesigner: | |
| status: | In Progress → Fix Committed |
| Changed in fsmdesigner: | |
| status: | Fix Committed → Fix Released |
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TODO:
- Add a common interface to store parameters inside the output XML