Better handling of unplated vias
Bug #699499 reported by
dkogan55
This bug affects 1 person
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
Fix Released
|
Medium
|
Unassigned |
Bug Description
The attached patch adds checks in the geometry intersection functions to no longer treat unplated vias (mounting holes) as conducting. The implementation in the patch will act as if the unplated via doesn't intersect with metal objects at all, which is possibly not what is desired. Should the conductivity check happen on a higher level from the geometry intersection routines? A case that would require this is not obvious to me.
Changed in pcb: | |
milestone: | future-bug-release → next-bug-release |
Changed in pcb: | |
status: | Fix Committed → Fix Released |
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I think a better fix would be to make a no-go net, and cause the mounting holes to conduct that net. Any connection to the no-go net would cause a DRC failure as well as anything being too close to the no-go net.