various issues with busses in Verilog back end

[jetrull]

I know of three problems with the Verilog back end related to bussed wires and I/Os:

1) bussed outputs appear in the port listing twice: once as inputs, once as outputs
2) single-bit busses whose only bit is 0 appear as scalars without an index in the port list
3) instance names with square brackets are not escaped

An example schematic is attached.

Regards,
Jeff Trull