Does not use existing/modified VHDL in creating VHDL of instances

[themusicgod1]

Binary package hint: electric

For some reason, spurious "signals" occasionally show up in the VHDL made with the "Make VHDL"
You can fix those in the VHDL by inspection. That's not really what this bug is about though, since you can get around that.

What happens is that the VHDL generated by 'Make VHDL' from schematic view uses the schematic view-level data from the problem cell, including spurious signals, from wherever those are coming from. This means that every time you build something with that cell electric "forgets" everything that you've changed in the VHDL view.

Spurious signals aren't the only problem here -- if you make your VHDL more readable by changing the "net_NNN" signal names to something more meaningful, if you create a new instance of this component it immediately throws away all that information.

What should happen:
If VHDL is generated from an instance of a cell with VHDL that is different from the schematic view, then the VHDL should be taken from that VHDL file. Or at the very least, there should be an option of this. (And if there is it should be easier to locate)
(Electric 8.08/jaunty)

ProblemType: Bug
Architecture: amd64
DistroRelease: Ubuntu 9.04
Package: electric 8.08-1
PackageArchitecture: all
ProcEnviron:
 PATH=(custom, user)
 LANG=en_CA.UTF-8
 SHELL=/bin/bash
SourcePackage: electric
Uname: Linux 2.6.28-16-generic x86_64