From a2f22dcbfd3c5135d0cdf148870d1da3254c3919 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Fri, 20 May 2022 13:38:33 +0200 Subject: [PATCH] s390-tools/lscpumf: Add support for IBM z16 extended counter set Add support for IBM z16 extended counter set to lscpumf. Signed-off-by: Thomas Richter --- cpumf/Makefile | 2 +- cpumf/bin/cpumf_helper.in | 4 +- cpumf/data/cpum-cf-extended-z16.ctr | 501 ++++++++++++++++++++++++++++ cpumf/data/cpum-cf-hw-counter.map | 2 + 4 files changed, 507 insertions(+), 2 deletions(-) create mode 100644 cpumf/data/cpum-cf-extended-z16.ctr diff --git a/cpumf/Makefile b/cpumf/Makefile index e97f20d..c7fc811 100644 --- a/cpumf/Makefile +++ b/cpumf/Makefile @@ -10,7 +10,7 @@ DATA_FILES = cpum-cf-hw-counter.map \ cpum-cf-extended-z10.ctr cpum-cf-extended-z196.ctr \ cpum-cf-extended-zEC12.ctr cpum-sf-modes.ctr \ cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr \ - cpum-cf-extended-z15.ctr + cpum-cf-extended-z15.ctr cpum-cf-extended-z16.ctr LIB_FILES = bin/cpumf_helper USRBIN_SCRIPTS = bin/lscpumf USRSBIN_SCRIPTS = bin/chcpumf diff --git a/cpumf/bin/cpumf_helper.in b/cpumf/bin/cpumf_helper.in index 988f2de..de1d7f1 100755 --- a/cpumf/bin/cpumf_helper.in +++ b/cpumf/bin/cpumf_helper.in @@ -212,6 +212,8 @@ my $system_z_hwtype_map = { 3906 => 'IBM z14', 3907 => 'IBM z14 ZR1', 8561 => 'IBM z15', + 8562 => 'IBM z15 Model T02', + 3931 => 'IBM z16', }; sub get_hardware_type() @@ -269,7 +271,7 @@ sub cpumf_load_ctrdef($;$) if ($version->{csvn} >= 1 && $version->{csvn} <= 6) { push @def, "csvn-12345"; } - if ($version->{csvn} == 6) { + if ($version->{csvn} >= 6) { push @def, "csvn-6"; } diff --git a/cpumf/data/cpum-cf-extended-z16.ctr b/cpumf/data/cpum-cf-extended-z16.ctr new file mode 100644 index 0000000..5b5794b --- /dev/null +++ b/cpumf/data/cpum-cf-extended-z16.ctr @@ -0,0 +1,501 @@ +Counter: 128 Name:L1D_RO_EXCL_WRITES +Short-Description:L1D Read-only Exclusive Writes +Description: +A directory write to the Level-1 Data cache where the line was +originally in a Read-Only state in the cache but has been updated +to be in the Exclusive state that allows stores to the cache line. +. +Counter: 129 Name:DTLB2_WRITES +Short-Description:DTLB2 Writes +Description: +A translation has been written into +The Translation Lookaside Buffer 2 (TLB2) and the +request was made by the Level-1 Data cache. This +is a replacement for what was provided for the DTLB +on z13 and prior machines. +. +Counter: 130 Name:DTLB2_MISSES +Short-Description:DTLB2 Misses +Description: +A TLB2 miss is in progress for a +request made by the Level-1 Data cache. +Incremented by one for every TLB2 miss in progress +for the Level-1 Data cache on this cycle. This is a +replacement for what was provided for the DTLB on +z13 and prior machines. +. +Counter: 131 Name:CRSTE_1MB_WRITES +Short-Description:One Megabyte CRSTE writes +Description: +A translation entry was written into +the Combined Region and Segment Table Entry +array in the Level-2 TLB for a one-megabyte page. +. +Counter: 132 Name:DTLB2_GPAGE_WRITES +Short-Description:DTLB2 Two-Gigabyte Page Writes +Description: +A translation entry for a two-gigabyte +page was written into the Level-2 TLB. +. +Counter: 134 Name:ITLB2_WRITES +Short-Description:ITLB2 Writes +Description: +A translation entry has been written +into the Translation Lookaside Buffer 2 (TLB2) and +the request was made by the instruction cache. This +is a replacement for what was provided for the ITLB +on z13 and prior machines. +. +Counter: 135 Name:ITLB2_MISSES +Short-Description:ITLB2 Misses +Description: +A TLB2 miss is in progress for a +request made by the Level-1 Instruction cache. +Incremented by one for every TLB2 miss in progress +for the Level-1 Instruction cache in a cycle. This is a +replacement for what was provided for the ITLB on +z13 and prior machines. +. +Counter: 137 Name:TLB2_PTE_WRITES +Short-Description:TLB2 Page Table Entry Writes +Description: +A translation entry was written into +the Page Table Entry array in the Level-2 TLB. +. +Counter: 138 Name:TLB2_CRSTE_WRITES +Short-Description:TLB2 Combined Region and Segment Entry Writes +Description: +Translation entries were written into +the Combined Region and Segment Table Entry +array and the Page Table Entry array in the +Level-2 TLB. +. +Counter: 139 Name:TLB2_ENGINES_BUSY +Short-Description:TLB2 Engines Busy +Description: +The number of Level-2 TLB translation engines busy in a cycle. +. +Counter: 140 Name:TX_C_TEND +Short-Description:Completed TEND instructions in constrained TX mode +Description: +A TEND instruction has completed in a constrained +transactional-execution mode. +. +Counter: 141 Name:TX_NC_TEND +Short-Description:Completed TEND instructions in non-constrained TX mode +Description: +A TEND instruction has completed in a non-constrained +transactional-execution mode. +. +Counter: 143 Name:L1C_TLB2_MISSES +Short-Description:L1C TLB2 Misses +Description: +Increments by one for any cycle +where a level-1 cache or level-2 TLB miss is in +progress. +. +Counter: 145 Name:DCW_REQ +Short-Description:Directory Write Level 1 Data Cache from Cache +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from the requestor’s Level-2 cache. +. +Counter: 146 Name:DCW_REQ_IV +Short-Description:Directory Write Level 1 Data Cache from Cache with Intervention +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from the requestor’s Level-2 cache with +intervention. +. +Counter: 147 Name:DCW_REQ_CHIP_HIT +Short-Description:Directory Write Level 1 Data Cache from Cache with Chip HP Hit +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from the requestor’s Level-2 cache after +using chip level horizontal persistence, Chip-HP hit. +. +Counter: 148 Name:DCW_REQ_DRAWER_HIT +Short-Description:Directory Write Level 1 Data Cache from Cache with Drawer HP Hit +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from the requestor’s Level-2 cache after +using drawer level horizontal persistence, Drawer-HP hit. +. +Counter: 149 Name:DCW_ON_CHIP +Short-Description:Directory Write Level 1 Data Cache from On-Chip Cache +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Chip Level-2 cache. +. +Counter: 150 Name:DCW_ON_CHIP_IV +Short-Description:Directory Write Level 1 Data Cache from On-Chip Cache with Intervention +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Chip Level-2 cache with +intervention. +. +Counter: 151 Name:DCW_ON_CHIP_CHIP_HIT +Short-Description:Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Chip Level-2 cache after using +chip level horizontal persistence, Chip-HP hit. +. +Counter: 152 Name:DCW_ON_CHIP_DRAWER_HIT +Short-Description:Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Chip Level-2 cache using +drawer level horizontal persistence, Drawer-HP hit. +. +Counter: 153 Name:DCW_ON_MODULE +Short-Description:Directory Write Level 1 Data Cache from On-Module Cache +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Module Level-2 cache. +. +Counter: 154 Name:DCW_ON_DRAWER +Short-Description:Directory Write Level 1 Data Cache from On-Drawer Cache +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an On-Drawer Level-2 cache. +. +Counter: 155 Name:DCW_OFF_DRAWER +Short-Description:Directory Write Level 1 Data Cache from Off-Drawer Cache +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from an Off-Drawer Level-2 cache. +. +Counter: 156 Name:DCW_ON_CHIP_MEMORY +Short-Description:Directory Write Level 1 Data Cache from On-Chip Memory +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from On-Chip memory. +. +Counter: 157 Name:DCW_ON_MODULE_MEMORY +Short-Description:Directory Write Level 1 Data Cache from On-Module Memory +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from On-Module memory. +. +Counter: 158 Name:DCW_ON_DRAWER_MEMORY +Short-Description:Directory Write Level 1 Data Cache from On-Drawer Memory +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from On-Drawer memory. +. +Counter: 159 Name:DCW_OFF_DRAWER_MEMORY +Short-Description:Directory Write Level 1 Data Cache from Off-Drawer Memory +Description: +A directory write to the Level-1 Data +cache directory where the returned cache line was +sourced from Off-Drawer memory. +. +Counter: 160 Name:IDCW_ON_MODULE_IV +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention +Description: +A directory write to the Level-1 Data +or Level-1 Instruction cache directory where the +returned cache line was sourced from an On-Module +Level-2 cache with intervention. +. +Counter: 161 Name:IDCW_ON_MODULE_CHIP_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit +Description: +A directory write to the Level-1 Data +or Level-1 Instruction cache directory where the +returned cache line was sourced from an On-Module +Level-2 cache using chip horizontal persistence, +Chip-HP hit. +. +Counter: 162 Name:IDCW_ON_MODULE_DRAWER_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit +Description: +A directory write to the Level-1 Data +or Level-1 Instruction cache directory where the +returned cache line was sourced from an On-Module +Level-2 cache using drawer level horizontal +persistence, Drawer-HP hit. +. +Counter: 163 Name:IDCW_ON_DRAWER_IV +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention +Description: +A directory write to the Level-1 Data +or Level-1 Instruction cache directory where the +returned cache line was sourced from an On-Drawer +Level-2 cache with intervention. +. +Counter: 164 Name:IDCW_ON_DRAWER_CHIP_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit +Description: +A directory write to the Level-1 Data +or Level-1 instruction cache directory where the +returned cache line was sourced from an On-Drawer +Level-2 cache using chip level horizontal persistence, +Chip-HP hit. +. +Counter: 165 Name:IDCW_ON_DRAWER_DRAWER_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit +Description: +A directory write to the Level-1 Data +or Level-1 instruction cache directory where the +returned cache line was sourced from an On-Drawer +Level-2 cache using drawer level horizontal +persistence, Drawer-HP hit. +. +Counter: 166 Name:IDCW_OFF_DRAWER_IV +Short-Description:Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention +Description: +A directory write to the Level-1 Data +or Level-1 instruction cache directory where the +returned cache line was sourced from an Off-Drawer +Level-2 cache with intervention. +. +Counter: 167 Name:IDCW_OFF_DRAWER_CHIP_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit +Description: +A directory write to the Level-1 Data +or Level-1 instruction cache directory where the +returned cache line was sourced from an Off-Drawer +Level-2 cache using chip level horizontal persistence, +Chip-HP hit. +. +Counter: 168 Name:IDCW_OFF_DRAWER_DRAWER_HIT +Short-Description:Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit +Description: +A directory write to the Level-1 Data +or Level-1 Instruction cache directory where the +returned cache line was sourced from an Off-Drawer +Level-2 cache using drawer level horizontal +persistence, Drawer-HP hit. +. +Counter: 169 Name:ICW_REQ +Short-Description:Directory Write Level 1 Instruction Cache from Cache +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced the requestors Level-2 cache. +. +Counter: 170 Name:ICW_REQ_IV +Short-Description:Directory Write Level 1 Instruction Cache from Cache with Intervention +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from the requestors Level-2 cache +with intervention. +. +Counter: 171 Name:ICW_REQ_CHIP_HIT +Short-Description:Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from the requestors Level-2 cache +using chip level horizontal persistence, Chip-HP hit. +. +Counter: 172 Name:ICW_REQ_DRAWER_HIT +Short-Description:Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from the requestor’s Level-2 cache +using drawer level horizontal persistence, Drawer-HP hit. +. +Counter: 173 Name:ICW_ON_CHIP +Short-Description:Directory Write Level 1 Instruction Cache from On-Chip Cache +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from an On-Chip Level-2 cache. +. +Counter: 174 Name:ICW_ON_CHIP_IV +Short-Description:Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced an On-Chip Level-2 cache with +intervention. +. +Counter: 175 Name:ICW_ON_CHIP_CHIP_HIT +Short-Description:Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from an On-Chip Level-2 cache +using chip level horizontal persistence, Chip-HP hit. +. +Counter: 176 Name:ICW_ON_CHIP_DRAWER_HIT +Short-Description:Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from an On-Chip level 2 cache +using drawer level horizontal persistence, Drawer-HP hit. +. +Counter: 177 Name:ICW_ON_MODULE +Short-Description:Directory Write Level 1 Instruction Cache from On-Module Cache +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from an On-Module Level-2 cache. +. +Counter: 178 Name:ICW_ON_DRAWER +Short-Description:Directory Write Level 1 Instruction Cache from On-Drawer Cache +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced an On-Drawer Level-2 cache. +. +Counter: 179 Name:ICW_OFF_DRAWER +Short-Description:Directory Write Level 1 Instruction Cache from Off-Drawer Cache +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced an Off-Drawer Level-2 cache. +. +Counter: 180 Name:ICW_ON_CHIP_MEMORY +Short-Description:Directory Write Level 1 Instruction Cache from On-Chip Memory +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from On-Chip memory. +. +Counter: 181 Name:ICW_ON_MODULE_MEMORY +Short-Description:Directory Write Level 1 Instruction Cache from On-Module Memory +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from On-Module memory. +. +Counter: 182 Name:ICW_ON_DRAWER_MEMORY +Short-Description:Directory Write Level 1 Instruction Cache from On-Drawer Memory +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from On-Drawer memory. +. +Counter: 183 Name:ICW_OFF_DRAWER_MEMORY +Short-Description:Directory Write Level 1 Instruction Cache from Off-Drawer Memory +Description: +A directory write to the Level-1 +Instruction cache directory where the returned cache +line was sourced from Off-Drawer memory. +. +Counter: 224 Name:BCD_DFP_EXECUTION_SLOTS +Short-Description:Binary Coded Decimal to Decimal Floating Point conversions +Description: +Count of floating point execution slots +used for finished Binary Coded Decimal to Decimal +Floating Point conversions. Instructions: CDZT, +CXZT, CZDT, CZXT. +. +Counter: 225 Name:VX_BCD_EXECUTION_SLOTS +Short-Description:Count finished vector arithmetic Binary Coded Decimal instructions +Description: +Count of floating point execution slots +used for finished vector arithmetic Binary Coded +Decimal instructions. Instructions: VAP, VSP, VMP, +VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, +VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, +VCVDG. +. +Counter: 226 Name:DECIMAL_INSTRUCTIONS +Short-Description:Decimal instruction dispatched +Description: +Decimal instruction dispatched. +Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, +MP, SRP, SP, ZAP. +. +Counter: 232 Name:LAST_HOST_TRANSLATIONS +Short-Description:Last host translation done +Description: +Last Host Translation done +. +Counter: 244 Name:TX_NC_TABORT +Short-Description:Aborted transactions in unconstrained TX mode +Description: +A transaction abort has occurred in a +non-constrained transactional-execution mode. +. +Counter: 245 Name:TX_C_TABORT_NO_SPECIAL +Short-Description:Aborted transactions in constrained TX mode +Description: +A transaction abort has occurred in a +constrained transactional-execution mode and the +CPU is not using any special logic to allow the +transaction to complete. +. +Counter: 246 Name:TX_C_TABORT_SPECIAL +Short-Description:Aborted transactions in constrained TX mode using special completion logic +Description: +A transaction abort has occurred in a +constrained transactional-execution mode and the +CPU is using special logic to allow the transaction to +complete. +. +Counter: 248 Name:DFLT_ACCESS +Short-Description:Cycles CPU spent obtaining access to Deflate unit +Description: +Cycles CPU spent obtaining access to Deflate unit +. +Counter: 253 Name:DFLT_CYCLES +Short-Description:Cycles CPU is using Deflate unit +Description: +Cycles CPU is using Deflate unit +. +Counter: 256 Name:SORTL +Short-Description:Count SORTL instructions +Description: +Increments by one for every SORT LISTS instruction executed. +. +Counter: 265 Name:DFLT_CC +Short-Description:Increments DEFLATE CONVERSION CALL +Description: +Increments by one for every DEFLATE CONVERSION CALL +instruction executed. +. +Counter: 266 Name:DFLT_CCFINISH +Short-Description:Increments completed DEFLATE CONVERSION CALL +Description: +Increments by one for every DEFLATE CONVERSION CALL +instruction executed that ended in Condition Codes 0, 1 or 2. +. +Counter: 267 Name:NNPA_INVOCATIONS +Short-Description:NNPA Total invocations +Description: +Increments by one for every Neural +Network Processing Assist instruction +executed. +. +Counter: 268 Name:NNPA_COMPLETIONS +Short-Description:NNPA Total completions +Description: +Increments by one for every Neural +Network Processing Assist instruction +executed that ended in Condition Codes 0, 1 or 2. +. +Counter: 269 Name:NNPA_WAIT_LOCK +Short-Description:Cycles spent obtaining NNPA lock +Description: +Cycles CPU spent obtaining access to +IBM Z Integrated Accelerator for AI. +. +Counter: 270 Name:NNPA_HOLD_LOCK +Short-Description:Cycles spent holding NNPA lock +Description: +Cycles CPU is using IBM Z Integrated +Accelerator for AI. +. diff --git a/cpumf/data/cpum-cf-hw-counter.map b/cpumf/data/cpum-cf-hw-counter.map index fec8048..8007ee5 100644 --- a/cpumf/data/cpum-cf-hw-counter.map +++ b/cpumf/data/cpum-cf-hw-counter.map @@ -30,4 +30,6 @@ 3907 => 'cpum-cf-extended-z14.ctr', 8561 => 'cpum-cf-extended-z15.ctr', 8562 => 'cpum-cf-extended-z15.ctr', + 3931 => 'cpum-cf-extended-z16.ctr', + 3932 => 'cpum-cf-extended-z16.ctr', }; -- 2.32.0