RISC-V Vector Instruction vssub.vv not saturating
Bug #1923629 reported by
Tony Cole
This bug affects 1 person
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Fix Released
|
Undecided
|
Frank Chang |
Bug Description
I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
Here is the bit of the code:
vmv.v.i v16, 0
…
8f040457 vssub.vv v8,v16,v8
I believe the instruction encoding is correct (vssub.vv with vd = v8, vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
I’ve just tested with what I think is the latest branch ( https:/
Changed in qemu: | |
status: | Fix Committed → Fix Released |
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Thanks for raising this bug case. A fix should be available soon.