Exynos4210 UART peripheral data loss
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Fix Released
|
Undecided
|
Unassigned |
Bug Description
Currently the Exynos4210 UART (hw/char/
Even worse, potentially enabling the FIFO without a FIFO reset will create a weird situation where data is already in the FIFO whenever data came in faster than the polling could pick it up (which is basically always).
This change obscured the issue in https:/
I have a patch ready for the bug and will submit it later today, I'm just filing for clarity.
commit 40b4c2ae90e4f86 4a1015ff748a4af 00518ff0c0