AArch64 EXT instruction for V register does not clear MSB side bits

[Kentaro Kawakami]

On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value.

Example
ext v0.16b, v1.16b v2.16b, 8

After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width.

[Richard Henderson (rth)]

Yep.

[Laurent Vivier (laurent-vivier)]

Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b

[Kentaro Kawakami (kawakami-k)]

Thank you for bug fix.
I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug.

[Richard Henderson (rth)]

All of those, and tbl, tbx, ins, are fixed in the three subsequent commits.