RISC-V mstatus TSR bit not correctly implemented
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Fix Released
|
Undecided
|
Unassigned |
Bug Description
Hi,
since qemu 4.1.0 the TSR bit in mstatus register is supported. But it does not allow for executing sret in m-mode.
From the RISC-V specifications:
"When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction
exception. When TSR=0, this operation is permitted in S-mode."
This means an exception should only be raised when executing in S-mode, but not in M-mode, hence you should change the condition in helper_sret (target/
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
to:
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
Fixed here: /git.qemu. org/?p= qemu.git; a=commitdiff; h=ed5abf46b3c4
https:/