ERC bus member warning on nightly

Bug #1831365 reported by DashieV3
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
KiCad
Fix Committed
Medium
Jon Evans

Bug Description

Was trying nightly (PPA, 6.0.0-unknown-27a2b84~100~ubuntu18.04.1) and I'm getting weird warnings in the ERC about BUS members:

"Bus to Wire Entry (...) is connected to Vertical Bus from (...) to (...) (X[Y..Z]) but is not a member of the bus"

The warnings seems present on every bus lines.

I've attached a quick schematic reproducing the issue.

Also related kicad forum topic: https://forum.kicad.info/t/kicad-nightly-erc-bus-member-warning/17343

Tags: eeschema erc
Revision history for this message
DashieV3 (dashie) wrote :
tags: added: eeschema erc
Changed in kicad:
milestone: none → 6.0.0-rc1
Jon Evans (craftyjon)
Changed in kicad:
assignee: nobody → Jon Evans (craftyjon)
Jon Evans (craftyjon)
Changed in kicad:
importance: Undecided → Medium
status: New → In Progress
Revision history for this message
KiCad Janitor (kicad-janitor) wrote :

Fixed in revision 256d7b07140a43cd6609920b3ec43e84202d2c0b
https://git.launchpad.net/kicad/patch/?id=256d7b07140a43cd6609920b3ec43e84202d2c0b

Changed in kicad:
status: In Progress → Fix Committed
Revision history for this message
DashieV3 (dashie) wrote :

Ok I confirm this fix the issue, now, in the test project, only A0 errors because it is connected nowhere (this is ok here).

But if I remove the two global labels, and connect the two bus between them, and re-run ERC, all the nets have an error "Bus to wire entry is connected to vertical bus from x to y <no net> but is not a member of the bus". (only one of the two labels for each Axx on the bus have that error)

Is this something expected or a bug (I can open another one then) ?

Revision history for this message
Jon Evans (craftyjon) wrote :

Can you post a screenshot or your updated design so that it is clear what is needed to reproduce the behavior you're describing?

Revision history for this message
DashieV3 (dashie) wrote :

Yes sorry, here is an updated zip project

Revision history for this message
Jon Evans (craftyjon) wrote :

OK, thanks.
This is expected behavior: Buses are not automatically labeled with their contents, so if you just draw graphical bus wires between a bunch of nets as is the case with your A[23..0] nets, there is no way to check whether or not the connection was intended.

To get rid of this error for now, you will need to properly label your bus. In the case of the example design, a label like "A[23..0]" will work.

Sometime during the V6 design cycle it will become possible to disable certain ERC checks if you don't want to label your buses for some reason.

Revision history for this message
DashieV3 (dashie) wrote :

Ok that makes sense, thank you for explanation !

Everything is good then.

To post a comment you must log in.
This report contains Public information  
Everyone can see this information.

Other bug subscribers

Remote bug watches

Bug watches keep track of this bug in other bug trackers.