Dangling wires no ERC error
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
KiCad |
Expired
|
Wishlist
|
Bug Description
Last time I have made mistake (like lot of other guys I suspect) in my schematic as I have forgotten to connect correctly GND to capacitors which are in parallel and unfortunately after ERC check there is no any error detected
I know it is a typical human error but it is very critical as we can produce invalid/buggy PCB and it could be detected easily by implementing a systematic "dangling wire" check in the whole schematic.
I have reproduced that with a very simple sample using latest KiCad 5.1.2-1 in Windows 7 64bits (I suspect it can be reproduced with any version of KiCad as such feature to detect dangling wire in ERC is not implemented today)
See picture of schematic for more details
https:/
See KiCad 5.1.2-1 project KiCad_dangling_
Changed in kicad: | |
assignee: | nobody → Jon Evans (craftyjon) |
milestone: | none → 6.0.0-rc1 |
importance: | Undecided → Wishlist |
status: | New → Triaged |
tags: |
added: eeschema removed: dangling error wires |
I'd upvote this if there were a way to do so. The problem is particularly frustrating when you have lots of passive component pins and have to use a smaller grid size. (I have to use 25 mils.) It's very tough to find ends of wires that are dangling 25 mils from a pin. I just had to deal with 3 schematics, each having 3 such errors in them, but no problem detected by ERC. Or at least, I _hope_ there were only 3 such errors each of those schematics!