RISC-V PLIC enable interrupt for multicore
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Invalid
|
Undecided
|
Unassigned |
Bug Description
Hello all,
There is a bug in Qemu related to the enabling of external interrupts for multicores (Virt machine).
After correcting Qemu as described in #1815078 (https:/
This works perfectly for core 0, but fore core 1 it does not work at all. I assume that given bug #1815078 does not enable any external interrupt then this feature has not been tested. I tried to look at the qemu source code but with no luck so far.
I guess the problem is related to function parse_hart_config (in sfive_plic.c) that initializes incorrectly the plic->addr_
Best regards,
Pharos team
Hi,
After some debugging (and luck), the problem (at least in the Virt board) was that the PLIC code inside QEMU addresses the core x 2 instead of just the core (core=hart). That is why it worked for core 0 (0x2 = 0) but for core 1 it has to address the PLIC memory area for core 2.
For example, the interrupt enable address for core 1 starts at offset 0x002080 (see https:/ /github. com/riscv/ riscv-plic- spec/blob/ master/ riscv-plic. adoc) but we actually have to change the enable bit for core 2 (at 0x002100) to make to work for core 1.
The same is true for the priority threshold and claim complete registers (we need to multiply the core by 2)
Either the documentation at https:/ /github. com/riscv/ riscv-plic- spec/blob/ master/ riscv-plic. adoc does not have the correct memory addresses for qemu virt board, or qemu appears to be wrong.