PNS router and half-castellation

[Simon Richter]

The PNS router disallows starting a trace on or outside the board edge, with a dialog "Cannot start routing inside a keep out area or board outline."

If the board edge passes through castellation vias, this means that traces cannot be started on these vias. Ending them there apparently works, and this is being passed around in user forums as a tip.

This probably needs an explicit exception so castellation vias can serve as start points.

[Wayne Stambaugh (stambaughw)]

I can understand the router doing this if the castellation via is outside the board edge but the logic should to be changed when the castellation via is bisected by the board edge.

[Tomasz Wlostowski (twlostow)]

@Wayne, I agree with Simon. How do we know if a via is a castellation via (without explicitly marking it as such somewhere in the design rules) or just a via that someone placed on the board edge by accident?

Moreover, boards routed using a workaround that checks if the edge board bisects castallation vias will still produce DRC errors (tracks too close to board edges). How about marking particular vias/pads/regions of the board as No DRC?

Tom

[Seth Hillbrand (sethh)]

Do we leave this as-is for 5.1? Any traces starting/ending on the edge will raise DRC errors.

[Seth Hillbrand (sethh)]

I'll push this to 6 when we can mark the castellation holes properly unless someone can think of a good way to bypass that currently

[Paul van der hoeven (paulvdh)]

I find it strange in this post that apparently via's are used for the castellations.
Usually these are in a straight row with regular spacing, and using a (purposely designed) THT footprint seems much more logical to me.

Recently this popped up again on the user forum:
https://forum.kicad.info/t/smd-pcb-modules-kicad-tutorial/17519

The basic limitation is here in KiCad not being "finished" yet, and not able to have an answer for all the "weird" things users want to do.

A very general solution would be to have a system to mark certain DRC errors, and those DRC errors would then be ignored by KiCad. It would be even better to have a text file with these errors and comments (entered by users) of why these errors are ignored.
DRC check already works with warnings & errors, and different colors, and fitting this in as an extra feature seems straightforward.

[blackketter (ppt-dean)]

I have found a related behavior where traces routed to castellated pads (starting at a non castellated origin) may be deleted when "Clean Up Tracks And Vias" is used with "Delete Dangling Tracks". It doesn't seem to happen all the time, which is a little weird. Should this be in a separate bug?

[Ian McInerney (imcinerney)]

@blackketter, please report that in a separate bug report with the version information & steps to treproduce (That seems to be a different issue than not being able to route from the pad).

[KiCad Janitor (kicad-janitor)]

KiCad bug tracker has moved to Gitlab. This report is now available here: https://gitlab.com/kicad/code/kicad/-/issues/1790