Hi,
running the Design Rule Check should not change the layout of your board.
Currently, as part of running the Pcbnew's DRC, the filled areas are recalculated.
If, due to some previous routing, there are overlaps with filled areas, it can lead to the situation displayed in the attached project.
Here, one trace overlaps a filled area.
Now, when running the DRC, this overlap is removed by recalculating the filled areas.
However, the DRC doesn't mention this in any way, so one can easily believe, that the design prior to executing the DRC was correct (and thus leads to ordering wrong layouts…).
In my opinion this is a user interface bug. I understand, that it might be necessary to recalculate the filled areas during the DRC. However, *if* this leads to changes, it should be clearly presented to the user. Maybe something similar to the way in which the user gets asked, if the annotations should be automatically updated, when she tries to export a netlist and some parts are not annotated.
Application: kicad
Version: 4.0.5+dfsg1-4 release build
wxWidgets: Version 3.0.2 (debug,wchar_t,compiler with C++ ABI 1010,GCC 6.3.0,wx containers,compatible with 2.8)
Platform: Linux 4.9.0-3-amd64 x86_64, 64 bit, Little endian, wxGTK
Boost version: 1.62.0
libcurl version: 7.52.1 (with SSL - GnuTLS/3.5.8)
USE_WX_GRAPHICS_CONTEXT=OFF
USE_WX_OVERLAY=OFF
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_WXPYTHON=ON
USE_FP_LIB_TABLE=HARD_CODED_ON
BUILD_GITHUB_PLUGIN=ON
An option needs to be added so users can disable the automatic zone refilling. If I open a board and make no changes, running the DRC may change my board due to changes in the zone filling algorithm which should not happen when the board has not been modified.