qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Fix Released
|
Undecided
|
Matthieu Bucchianeri |
Bug Description
According to "Signal Processing Engine (SPE) Programming Environments Manual" at
http://
c.f section 4.2.3 and also Figure 2-2.
When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.
Hence, some tests for MSR[SPV] in file target-
Namely, in the definitions of
1. GEN_SPEFPUOP_
2. gen_efsabs
3. gen_efsnabs
4. gen_efsneg
5. GEN_SPEFPUOP_
Note, the macro GEN_SPEFPUOP_
One more thing, afaict the macro GEN_SPEFPUOP_
efs- and efd- instructions, and will need to be split in two versions.
The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions
(e.g efdctui) will need to add a test for MSR[SPV].
(I've looked at today's HEAD-revision of target-
Changed in qemu: | |
assignee: | nobody → Matthieu Bucchianeri (matthieu-bucchianeri) |
status: | New → In Progress |
I have filed a broader ticket, Bug #1888918, reporting a very similar issue that leads to corruption/bad arithmetic when using double-precision & vector instructions.
I will be submitting a patch in the next few days that will also address this ticket.