4e0ec9a37a1bd0853d5b843613726bb669af5350 Remove inline decl on arch/x86/include/asm/msr.h file . arch/x86/include/asm/msr.h | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 7a79ee2..47c2962 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -90,7 +90,7 @@ static inline unsigned long long native_read_msr(unsigned int msr) return EAX_EDX_VAL(val, low, high); } -static inline unsigned long long native_read_msr_safe(unsigned int msr, +static unsigned long long native_read_msr_safe(unsigned int msr, int *err) { DECLARE_ARGS(val, low, high); @@ -108,7 +108,7 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr, return EAX_EDX_VAL(val, low, high); } -static inline void native_write_msr(unsigned int msr, +static void native_write_msr(unsigned int msr, unsigned low, unsigned high) { asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); @@ -117,7 +117,7 @@ static inline void native_write_msr(unsigned int msr, } /* Can be uninlined because referenced by paravirt */ -notrace static inline int native_write_msr_safe(unsigned int msr, +notrace static int native_write_msr_safe(unsigned int msr, unsigned low, unsigned high) { int err; @@ -148,7 +148,7 @@ extern int wrmsr_safe_regs(u32 regs[8]); * CPU can and will speculatively execute that RDTSC, though, so the * results can be non-monotonic if compared on different CPUs. */ -static __always_inline unsigned long long rdtsc(void) +static unsigned long long rdtsc(void) { DECLARE_ARGS(val, low, high); @@ -165,7 +165,7 @@ static __always_inline unsigned long long rdtsc(void) * be impossible to observe non-monotonic rdtsc_unordered() behavior * across multiple CPUs as long as the TSC is synced. */ -static __always_inline unsigned long long rdtsc_ordered(void) +static unsigned long long rdtsc_ordered(void) { /* * The RDTSC instruction is not ordered relative to memory @@ -213,7 +213,7 @@ do { \ (void)((high) = (u32)(__val >> 32)); \ } while (0) -static inline void wrmsr(unsigned msr, unsigned low, unsigned high) +static void wrmsr(unsigned msr, unsigned low, unsigned high) { native_write_msr(msr, low, high); } @@ -221,13 +221,13 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high) #define rdmsrl(msr, val) \ ((val) = native_read_msr((msr))) -static inline void wrmsrl(unsigned msr, u64 val) +static void wrmsrl(unsigned msr, u64 val) { native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); } /* wrmsr with exception handling */ -static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) +static int wrmsr_safe(unsigned msr, unsigned low, unsigned high) { return native_write_msr_safe(msr, low, high); } @@ -242,7 +242,7 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) __err; \ }) -static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) +static int rdmsrl_safe(unsigned msr, unsigned long long *p) { int err; @@ -264,7 +264,7 @@ do { \ /* * 64-bit version of wrmsr_safe(): */ -static inline int wrmsrl_safe(u32 msr, u64 val) +static int wrmsrl_safe(u32 msr, u64 val) { return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); } @@ -292,58 +292,58 @@ int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ -static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) +static int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) { rdmsr(msr_no, *l, *h); return 0; } -static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) +static int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { wrmsr(msr_no, l, h); return 0; } -static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) +static int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { rdmsrl(msr_no, *q); return 0; } -static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) +static int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { wrmsrl(msr_no, q); return 0; } -static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, +static void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr *msrs) { rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); } -static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, +static void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr *msrs) { wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); } -static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, +static int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) { return rdmsr_safe(msr_no, l, h); } -static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) +static int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { return wrmsr_safe(msr_no, l, h); } -static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) +static int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { return rdmsrl_safe(msr_no, q); } -static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) +static int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { return wrmsrl_safe(msr_no, q); } -static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +static int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { return rdmsr_safe_regs(regs); } -static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +static int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { return wrmsr_safe_regs(regs); } -- 2.7.4