Bugs in conformation check

Bug #1525159 reported by Danil Sokolov
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
Workcraft
Fix Committed
High
Danil Sokolov

Bug Description

There are several assumption for conformation check:
  1) For every SIGNAL of the dev STG there are places named SIGNAL_0 and SIGNAL_1.
  2) All the places of the dev STG are preserved in the composed (dev+env) STG.

Sometimes, when there are redundant places in the composed STG, PComp removes those places that came from the dev STG. As a result the conformation check becomes invalid.

For example, consider the attached AND-stg.work. A circuit (AND-fate) synthesised from this STG does not pass the conformation check. This is because place p0 of the env STGand place c_0 of the dev STG have the same preset and postset, and therefore one of them is redundant. PComp chooses to remove place c_0 and preserve p0. This breaks the above assumptions...

A quick fix is to rename place p0 in the env STG into c_0. This will ensure that place c_0 (either form the dev or from the env) is present in the composed STG.

Tags: circuit stg
Revision history for this message
Danil Sokolov (danilovesky) wrote :
Changed in workcraft:
status: Confirmed → Fix Committed
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