On Verilog import the initial state of signals in not read in Windows

Bug #1513019 reported by Danil Sokolov
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
Workcraft
Fix Committed
Medium
Danil Sokolov

Bug Description

The initial state of signals is encodded as the following kind of Verilog comment:
    // initial values of the signals
    // !oc !uv !zc gn_ack !gp_ack gn !gp

It is read properly in Linux, but not in Windows.
The most likely reason for this is the different encoding of new line: \n in Linux and \n\r in Windows.

Tags: circuit import
Changed in workcraft:
importance: Undecided → Medium
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