qemu-i386 pentium3/athlon incorrect instruction set

[PeteVine]

Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 from 20150609 using the -cpu pentium3 switch results in flawless execution whereas it should crash with SIGILL as P3 only had SSE and not SSE2.

[PeteVine (davine-k)]

Still there in the latest master.

To clarify, running the binary with the -cpu athlon switch (same instruction set as P3) also exhibits the problem whereas a real athlon SIGILL's correctly.

[Paolo Bonzini (bonzini)]

QEMU doesn't try to mimic the exact set of instructions for a processor, unfortunately. Virtualization solutions like KVM also do not allow you to do that, so the case for this feature is relatively minor.

However, patches are welcome.

[PeteVine (davine-k)]

I'm pretty sure you're right regarding entire instruction sets - but surely simply disabling SSE2 is possible even now? (after all pentium2 and below doesn't have it)

That could solve this problem with a simple hack like, eg. :

pentium3 = $pentium3 - SSE2

[PeteVine (davine-k)]

In the case it's really unfixable and both pentium3 and athlon are nothing more than aliases for 'QEMU Virtual CPU version 2.4.50' they should be removed from the list the user gets after:

qemu-i386 -cpu help

so as not to mislead. Thanks!

[PeteVine (davine-k)]

After looking at target-i386/cpu.c, it's clear to me CPUID_SSE and CPUID_SSE2 are defined seperately and neither pentium3 nor athlon have those defines set.

This could mean it's a bug not in the instruction set but possibly in the build process somewhere.

[Marina Kovalevna (ciiiiipa)]

This option is useful for testing, nothing more.

[PeteVine (davine-k)]

I think I may have found the culprit - athlon is defined as 'PPRO_FEATURES + some additional features'.

If PPRO_FEATURES is what I think it is (pentium pro) why does it have SSE and SSE2 defined? It should end with MMX.