Circuit STG has redundant transitions

Bug #1413679 reported by Danil Sokolov
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
Workcraft
Fix Committed
Medium
Danil Sokolov

Bug Description

The STG generated from a circuit may have unnecessary transitions. This is because the gate set/reset functions are not minimised before mapping them into STG.

Consider the attached circuit (it's an implementation of a C-element). In the STG obtained by WC there are 3 out+ and 4 out- transitions (should be one of each). Moreover, some of these transitions are dead due to having both places out=0 and out=1 in their presets.

A correct way for minimisith the STG complexity can be found on page 9 of:
http://dx.doi.org/10.1016/j.entcs.2008.12.101

Tags: circuit stg

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Revision history for this message
Danil Sokolov (danilovesky) wrote :
Revision history for this message
Danil Sokolov (danilovesky) wrote :

The gate is translated to a circuit Petri net without looking at its context. The read arcs are added at a later stage and in presence of self-loops redundant transitions are possible. I am not sure if this needs to be corrected.

Changed in workcraft:
status: Confirmed → Opinion
importance: Medium → Low
Changed in workcraft:
status: Opinion → In Progress
importance: Low → Medium
milestone: none → 3.0.4
Changed in workcraft:
status: In Progress → Fix Committed
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