[FEATURE]: detect mtrr default value

Bug #1322526 reported by Alex Hung
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
Firmware Test Suite
Fix Released
Undecided
Alex Hung

Bug Description

mtrr tests show error messages as below:
  mtrr: Memory range 0x1000 to 0x5efff (System RAM) has incorrect attribute Default (Most probably Uncached).

According to HP's BIOS engineer in UEFI Plugfest, HP's specifies default to "write-back", and therefore the error can be false positive. fwts should also detect whether default is specified in CPU.

Alex Hung (alexhung)
Changed in fwts:
assignee: nobody → Alex Hung (alexhung)
Revision history for this message
Alex Hung (alexhung) wrote :

According to Intel's 64-ia-32-architectures-software-developer-vol-3a-3b-system-programming-manual, Section 11.5.1 defines CR0's two bits, NW and CD, that control system-wide catch behaviours, i.e. "If the NW and CD flags are clear, write-back is enabled for the whole of system memory". The definition of CR0 and these two bits can also be found in Section 2.5.

Changed in fwts:
status: New → In Progress
Revision history for this message
Alex Hung (alexhung) wrote :

More information for NW and CD as below:

CD: Cache Disable (bit 30 of CR0) - When the CD and NW flags are clear,
caching of memory locations for the whole of physical memory in the
processor's internal (and external) caches is enabled. When the CD flag is
set, caching is restricted as described in Table 11-5. To prevent the processor
from accessing and updating its caches, the CD flag must be set and the
caches must be invalidated so that no cache hits can occur.

NW: Not Write-through (bit 29 of CR0) - When the NW and CD flags are
clear, write-back (for Pentium 4, Intel Xeon, P6 family, and Pentium proces-
sors) or write-through (for Intel486 processors) is enabled for writes that hit
the cache and invalidation cycles are enabled. See Table 11-5 for detailed
information about the affect of the NW flag on caching for other settings of
the CD and NW flags.

Revision history for this message
Colin Ian King (colin-king) wrote :

@Alex, any further progress on this bug?

Alex Hung (alexhung)
summary: - [FEATURE]: detect mtrr default value
+ [FEATURE]: detect mtrr default value
Revision history for this message
Alex Hung (alexhung) wrote :

It seems that IA32_MTRR_DEF_TYPE MSR can also serve a default:

The IA32_MTRR_DEF_TYPE MSR (named MTRRdefType MSR for the P6 family processors) sets the default properties of the regions of physical memory that are not encompassed by MTRRs. The functions of the flags and field in this register are as follows:

Type field, bits 0 through 7 - Indicates the default memory type used for those physical memory address ranges that do not have a memory type specified for them by an MTRR (see Table 11-8 for the encoding of this field). The legal values for this field are 0, 1, 4, 5, and 6. All other values result in a general-protection exception (#GP) being generated.

Intel recommends the use of the UC (uncached) memory type for all physical memory addresses where memory does not exist. To assign the UC type to nonexistent memory locations, it can either be specified as the default type in the Type field or be explicitly assigned with the fixed and variable MTRRs.

Revision history for this message
Alex Hung (alexhung) wrote :

Kernel reads IA32_MTRR_DEF_TYPE MSR in arch/x86/kernel/cpu/mtrr/generic.c and output the default to dmesg, ex. MTRR default type: write-back

Revision history for this message
Alex Hung (alexhung) wrote :

This is fixed by commit ebf64e50b49ab5c0b138ffee910c20c0caa1b7ac in fwts 16.07.00

Changed in fwts:
status: In Progress → Fix Released
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