broken verilog bufif symbols

[Alex-Daniel Jakimenko]

I have found a bug with verilog symbols bufif1-1.sym and bufif0-1.sym. For some reason gnetlist is not respecting the pinseq order, so the way they appear in the parameter list is determined by the order in .sym file, which is wrong currently:
INW, OUTW, CONTROLW

When it should be:
OUTW, INW, CONTROLW

This leads to broken simulations.

I have attached a patch to fix this issue.

[Vladimir Zhbanov (vzhbanov)]

Hi, Alex.
Could you provide a link to any document which can confirm the
order of pins you've used for these symbols is right?

Thanks,
  Vladimir

[Vladimir Zhbanov (vzhbanov)]

I mean, of course the order in the resulting netlist.

[Alex-Daniel Jakimenko (alex-jakimenko+launchpad)]

http://sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.pdf
8.0 Primitive Instances (Page 19)
bufif0, bufif1, notif0, notif1 - (1–output, 1–input, 1–control)

You can also look at pinseq number, which confirms it as well.

I'm glad you asked it, because I've just noticed that notif symbols are wrong as well.

I am attaching one more patch to fix notif symbols.

[gpleda.org commit robot (gpleda-launchpad-robot)]

Bug was fixed by a commit
git master commit 3f0987e69b1736a96977966f6a3eec72cfa7fe1d
http://git.geda-project.org/geda-gaf/commit/?id=3f0987e69b1736a96977966f6a3eec72cfa7fe1d

commit 3f0987e69b1736a96977966f6a3eec72cfa7fe1d
Author: Alex Jakimenko <email address hidden>
Commit: Vladimir Zhbanov <email address hidden>

    gnetlist: fixed pin order of notif verilog symbols

    Closes-bug: lp-1304681

[gpleda.org commit robot (gpleda-launchpad-robot)]

A commit was made which affects this bug
git master commit b7f86664c70ddc920c0055841fed55aee4aa730b
http://git.geda-project.org/geda-gaf/commit/?id=b7f86664c70ddc920c0055841fed55aee4aa730b

commit b7f86664c70ddc920c0055841fed55aee4aa730b
Author: Alex Jakimenko <email address hidden>
Commit: Vladimir Zhbanov <email address hidden>

    gnetlist: fixed two bufif symbols

    As the gnetlist verilog backend does not respect pinseq numbers, this
    results in a wrong parameter order inside produced verilog files.

    Affects-bug: lp-1304681