Clock initial state reversed
Bug #1265519 reported by
Johannes Mittendorfer
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| gLogic |
New
|
Undecided
|
Unassigned | ||
Bug Description
When doing some simulations I noticed that the initial state of the clock input is reverse in the time graph. So, when you need a initial state of low you set the initial state of the clock to high and vice versa.
| description: | updated |
Revision history for this message
| PsySc0rpi0n (psysc0rpi0n) wrote | #1 |
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No fixes to this bug? Since 2014?
I can also see Initial state reversed. I'm using Debian Buster and glogic version from reopsitories which is 2.6