pcb

DRC reports non-existent errors when using arcs for tracks

Bug #1229300 reported by doragasu
12
This bug affects 2 people
Affects Status Importance Assigned to Milestone
pcb
Fix Released
Medium
Chad Parker

Bug Description

When arcs are used to make tracks, DRC reports errors that don't exist. For example in the attached image, there is a small arc connecting two lines. The clearance is 7 mils, and even though there are around 8 mils from the track to the nearest pad, a DRC error is reported. This is reported for a lot more tracks using arcs like the one in the screenshot.

Tags: drc pcb
Revision history for this message
doragasu (doragasu) wrote :
Peter TB Brett (peter-b)
Changed in geda:
status: New → Invalid
Traumflug (mah-jump-ing)
Changed in geda-project:
importance: Undecided → Medium
summary: - pcb: DRC reports non-existent errors when using arcs for tracks
+ DRC reports non-existent errors when using arcs for tracks
no longer affects: geda
Revision history for this message
Chad Parker (parker-charles) wrote :

I know this was reported a long time ago, but, is there any chance of the OP providing the .pcb file that generates these errors?

Revision history for this message
doragasu (doragasu) wrote :

You can find the PCB under the sch/rev-B directory of this GitHub repository: https://github.com/doragasu/Balsamo

Unfortunately I am not using geda anymore, and I do not know if the error is still happening with latest version.

Revision history for this message
Chad Parker (parker-charles) wrote :

Thanks for posting the file. I'll look into it.

Revision history for this message
Chad Parker (parker-charles) wrote :

It looks like there is still something funny going on with the arcs. I think it's in the geometry calculations.

Changed in pcb:
importance: Undecided → Medium
assignee: nobody → Chad Parker (parker-charles)
milestone: none → pcb-4.2.0
status: New → Confirmed
Revision history for this message
Chad Parker (parker-charles) wrote :

This file has been very helpful, thank you for posting it!

I think the recent DRC fixes have fixed many of the issues you see with this board.

In many cases, there are traces of width 8 mil that join, but when you zoom way in, you can see that the points aren't precisely aligned (turn on thin-draw). With the "minimum copper overlap" set to 8 mils, anything other than perfect alignment is *technically* a violation.

Given the settings, I believe the DRC is now doing the right thing.

It does identify several places where there are minimum spacing violations. I've spot checked a few of these, and I can convince self that many of these cases are nearly exactly the minimum spacing. In fact, if you change it from 8.00 to 7.99 mils, the vast majority of them go away.

Ultimately this is because of the way that the detection is done (by bloating objects and checking for connectivity). pcb considers objects with 0 width between them to be touching. So, any spacing that is exactly the width of the setting will be identified as a violation.

At some point in the future, we may change the method for detecting these violations, at which time exact spacing may be considered okay, but for now, this will remain a violation.

I'm going to marking this as solved.

Changed in pcb:
status: Confirmed → Fix Committed
Changed in pcb:
status: Fix Committed → Fix Released
Changed in geda-project:
status: New → Fix Released
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