default silk layer names are the same for top and bottom
Bug #1035979 reported by
KaiMartin
This bug affects 2 people
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
Fix Released
|
Medium
|
Bert Timmerman |
Bug Description
The default layer stack as set by PCB for a new layout contains two silk layers. Both of them bear the same name "silk". The name does not actually show in the GUI. Still, it is irritating when editing the pcb file manually. In addition, the duplicate name complicates scripted manipulation of the file.
The attached patch sets the default name to "top silk" and "bottom silk" respectively.
---<)kaimartin(>---
Changed in pcb: | |
importance: | Undecided → Medium |
status: | In Progress → Fix Committed |
Changed in pcb: | |
milestone: | none → next-bug-release |
Changed in geda-project: | |
importance: | Undecided → Medium |
status: | New → Fix Released |
Changed in pcb: | |
status: | Fix Committed → Fix Released |
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HI Kai-Martin,
The patch seems to work as expected.
Kind regards,
Bert Timmerman.