Make genverilog v1 full intersection calculation switchable
Bug #1017548 reported by
Richard Leys
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | ||
|---|---|---|---|---|---|---|
| FSMDesigner | Status tracked in 5.2 | |||||
| 5.1 |
Fix Released
|
Critical
|
Unassigned | |||
| 5.2 |
Fix Released
|
Critical
|
Richard Leys | |||
Bug Description
The Genverilog v1 verilog generator can calculate all the cases intersections to write a completely defined case out.
This avoids warnings in some synthesis tools (Cadence RTL compiler for example), but can lead to very high generation times, and maybe some wrongly synthesised structures (seen on Xilinx ISE).
This feature is now switchable over a generator parameter
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